It is speculated that Intel's Larrabee (a throughput-optimized many-core implementation of the x86 architecture) will be well-suited to the role of a PPU; like the Cell, it sits between the CPU and the GPU in the spectrum of general purpose processing versus specialized high-performance back-end processing. Intel has confirmed that Larrabee's memory architecture will not use scratchpads like the Cell or Ageia PPU, and will instead be closer to a conventional CPU cache hierarchy. However, it will have extensions to enable high-throughput computing (most likely a full complement of cache-control instructions).
AMD have declared their long term intention to use the ATI GPU as a vector coprocessor more closely tied to the CPU, sharing resources such as cache hierarchy. This future configuration is also very likely to be suitable for the role of a PPU.
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